1. Field of the Invention
The present invention relates generally to switched-capacitor systems and, more particularly, to differential amplifiers in such systems.
2. Description of the Related Art
FIG. 1 illustrates a switched-capacitor system 20 in which a sample capacitor Cs has a top plate 21 coupled to the inverting input of a differential amplifier 22 and a bottom plate 23 coupled through an input sample switch 24 to an input port 25. The differential amplifier 22 drives an output port 26 and a transfer capacitor Ct is coupled across the differential amplifier. The differential amplifier has a high gain so that its non-inverting input has substantially the same potential as its inverting input. Finally, a second sample switch 27 and a transfer switch 28 are respectively coupled to the top and bottom plates 21 and 23.
In an operational sample mode, the input and second sample switches 24 and 27 are closed so that an analog input signal Sin at the input port 25 urges a sample charge Qs into the sample capacitor Cs to thereby acquire a sample signal Ss=Qs/Cs across the sample capacitor. In an operational transfer mode, the first and second sample switches 24 and 27 are opened and the transfer switch 28 is closed to transfer the sample charge Qs into the transfer capacitor Ct and thus generate an output signal Sout=Qs/Ct at the output port 26.
The switched-capacitor system 20 of FIG. 1 is thus formed with the differential amplifier 22 and a switched-capacitor structure 29 that incudes the sample and transfer capacitors Cs and Ct. The switched-capacitor structure 29 acquires a sample signal Ss in a sample mode and the differential amplifier processes the sample signal Ss into the output signal Sout across the output capacitor during the transfer mode. A transfer function of Cs/Ct is thus realized and this transfer function is represented in the graph 30 of FIG. 2 by a plot 32 which has a slope of Cs/Ct.
The switched-capacitor system 20 (and differential versions thereof) is especially suited for use as a sampler in a variety of signal conditioning systems (e.g., pipelined analog-to-digital converters (ADCs)). In such systems, the switches of the system 20 of FIG. 1 are typically realized with complementary metal-oxide-semiconductor (CMOS) transistors. This realization is exemplified in FIG. 1 by a CMOS transistor 34 that is substituted for the input sample switch 24 as indicated by the substitution arrow 35.
In pipelined ADCs, an initial ADC stage (e.g., a flash ADC) typically converts an analog input signal into at least one most-significant bit Do of a digital output signal that corresponds to the input signal Sin. At the same time, the sampled signal is processed into a residue signal Sres that is suitable for subsequent processing by downstream ADC stages into the less-significant bits of the output digital signal.
If the initial ADC stage is a 1.5 bit converter stage, for example, it provides a residue signal Sres that corresponds to the plot 36 in FIG. 2 which has two steps 37 that are equally spaced from the midpoint of the range of the input signal Sin. The steps are initiated by decision signals from the initial ADC stage. The plot 36 of the residue signal Sres, therefore, has three segments defined by the steps 37 and each segment has a slope that is twice the slope of the plot 32.
The residue signal illustrated by the plot 36 can be generated, for example, by supplementing the sample capacitor Cs of FIG. 1 with an additional sample capacitor to realize the increased slope (i.e., increased gain) and by replacing the transfer switch 28 with a multipole transfer switch 38 as indicated by the substitution arrow 39. The transfer switch responds to digital decision signals Sdgtl from the initial ADC stage by applying selected offset signals (e.g., +V and xe2x88x92V) to the bottom plate of at least one of the sample capacitors and the offset signals generate the steps 37 in the plot 32 of FIG. 2. When the switched-capacitor system 20 of FIG. 1 is modified in this fashion, it is typically referred to as a multiplying digital-to-analog converter (MDAC).
The operational speed of switched-capacitor systems (e.g., samplers and MDACs) is highly dependent upon the ability of an associated operational amplifier (e.g, the amplifier 22 of FIG. 1) to rapidly transfer the sample charge Qs in the sample capacitor Cs into the transfer capacitor Ct during the transfer mode. Although operational amplifiers often incorporate slew current strucutures to speed up this charge transfer, they typically (e.g., see Michaslki, Christopher, xe2x80x9cA 12b 105 Msample/S, 850 mW Analog to Digital Converterxe2x80x9d, VLSI Symposia on Circuits held in 2000 in Hawaii, USA) introduce intermediate structures (e.g., current mirrors) that degrade the speed of the transfer process.
The present invention is directed to high-speed differential amplifiers for use with switched-capacitor structures. These amplifiers reduce current demand during small-signal operation and generate high slew currents during large-signal operation.
These processes are realized with slew-current generation structures that directly generate slew currents during large-signal operation and thus avoid the degradation of intermediate current-genration structures.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.